6. Illustrative example: a time-delayed Chua’s circuit
The time-delayed Chua’s circuit represented on Figure 6.1 is composed of a realistic model of a linearized diode (see Figure 5.1) and a block made of an ideal line with a resistor in series [33]. Using (4.4) with , where is a time constant, the impedance of this block is computed as:
Both the numerator and the denominator of are quasi-polynomials of neutral type and since , it is easily checked that their roots lie on the vertical axis . Thus, this block is realistic. This provides us with an alternative model of a realistic line: an ideal line in series with a resistor.
Since this linearized circuit is made of realistic components, by Proposition 1 and Lemma 1, the impedance measured at the red dot on Figure 6.1 is well-defined, meromorphic and for , it is bounded outside a compact set. From Theorem 1, it has at most a finite number of unstable poles. Checking stability to small current perturbations at this node, amounts to determine whether has or not unstable poles. For this purpose, the method proposed in [23] and numerically implemented in [34], based on the stable/unstable decomposition (2.9), can be used. In the present example, was determined on 1500 points between 0 and 9 GHz. The results are shown on Figure 6.2 and the circuit is clearly unstable. In addition, poles in the right half-plane have been identified using the Principal Hankel Components algorithm (PHC) [35]: two expected poles at 2 GHz and two positive real poles (at DC). Details can be found in the conference paper [24].
Figure 6.1 Time-delayed Chua’s circuit made of realistic linearized electronic components.
Figure 6.2 Stability analysis tractable: the impedance determined at the location of the red dot has a finite number of unstable poles.
Beyond the simplicity of this illustrative example, the method apply to any time-delayed system of this type, as soon as it is obtained from realistic linearized electronic components.