5. Realistic active devices

Active devices are modeled as a combination of a non-linear intrinsic device surrounded by a linear package, or extrinsic network [30][31]. The extrinsic part of the model is a passive circuit, so the package model should satisfy Definition 3.1 to be realistic. In this section, we discuss realistic intrinsic models for diodes and transistors.

The intrinsic part of a transistor is modeled as a lumped circuit. Distributed effects, like non-quasi-static behavior are commonly included using rational approximations [31][32]. The linearisation of the intrinsic part will therefore result in a rational $Y$ or $Z$ matrix and is hence meromorphic everywhere on the complex plane.

5.1 Realistic diode models

The linearisation around an operating point for most diodes will result in a passive dipole, so a realistic model for such a diode should satisfy Definition 3.1. The linearisation of a tunnel diode, on the other hand, can exhibit a negative real part on the $j\omega$-axis for some operating points. A realistic tunnel diode cannot stay active for all frequencies, there should be a cutoff frequency where the dipole becomes passive: its complex impedance $Z$ and complex admittance $Y$ should satisfy the property that there is $\omega_{c}$ such that, whenever $|s|>\omega_{c}$ and $\Re(s)\ge 0$, then $\Re(Y(s))\ge\alpha$ and $\Re(Z(s))\ge\beta$, for some $\alpha,\beta>0$. Both diode models proposed in Figure 5.1 satisfy this property, but many other, more complex models could also be used.

Figure 5.1 Two realistic models of a linearized diode. Left: With inductive effect and high resistance. Right: With capacitive effect and small resistance.

5.2 Realistic CMOS transistor model

Transistors can also be modeled in a realistic way, to account for the fact that actual devices have no gain anymore at very high frequencies. As an example on how to determine whether a given transistor model is realistic, consider the model for a linearised CMOS transistor in a common-source configuration as presented in Figure 5.2. We will show that this simple model only satisfies condition (i) of Definition 1. To do so, we start by determining the $Y$-matrix of the circuit. We obtain the following relation for the transistor without $r_{g}$:

In terms of $y(s)$, the admittance matrix of the complete circuit is expressed as:

To determine whether $Y\!\left(s\right)$ is Y-realistic, we compute its asymptotic expansion at infinity

Checking that the principal minors of the asymptotic expansion of $Y(s)+Y^{*}(s)$ deduced from (5.1) are bounded away from zero for $\Re(s)\geq0$, yields that, under the assumption that $g_{d}>0$, there exists $\omega_{0}$ such that for $|s|>\omega_{0}$ and $\Re(s)\geq0$ the matricial inequality $Y(s)+Y^{*}(s)\geq\gamma{\bf Id}$ holds for some $\gamma>0$, which confirms that the model is Y-realistic. Note that this model could be rendered Z-realistic, and therefore completely realistic, by adding a resistor in series at the drain of the device.

Figure 5.2 Y-realistic model of a linearized CMOS transistor in common-source configuration.