A 42-GS/s, 7-bit 16nm Massively Time-Interleaved Slope-ADC
E. Martens, A. Cooman, P. Renukaswamy, S. Nagata, S. Park, J. Lagos Benites, N. Markulic, and J. Craninckx.
Proceedings of the International Solid-State Circuits Conference (ISSCC), Feb. 2024
For wireline receivers, ADCs with a resolution of 6 to 8 bits and a sampling speed of several tens of GHz are often required. To achieve these extremely high speeds, time-interleaved (TI) ADCs with tens of parallel high-speed channels are commonly used. SAR-based sub-ADCs are a popular choice due to their power-efficient architecture. Although SAR ADCs can be small, the need for a DAC and high-speed logic nevertheless results in a significant total area with long interconnection lines. This work introduces an alternative approach for extreme high-speed ADCs based on the paradigm that a slow-speed but extremely small channel allows for a more efficient conversion per area. By arranging them in a 2-dimensional array, interconnections are minimized, and power burned in parasitics is reduced resulting in an energy-efficient and scalable architecture.